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September 12, 2022 04:11 am GMT
Interestingly, the same leak also claims that the AD107, the fourth largest silicon powering lower mid-range SKUs, and which succeeds the GA107, features the same PCIe lane-count of x8. This is unlike AMD, which gives the "Navi 24" silicon a PCI-Express 4.0 x4 interface. Lowering the PCIe lane count simplifies PCB design, since there are fewer PCIe lanes to be wired out in precise trace-lengths to avoid asynchrony. It also reduces the pin-count of the GPU package. NVIDIA's calculation here is that there are now at least two generations of Intel and AMD platforms with PCIe Gen 4 or later (Intel "Rocket Lake" and "Alder Lake," AMD "Zen 2," and "Zen 3,") and so it makes sense to lower the PCIe lane-count.
Original Link: https://www.techpowerup.com/298768/nvidias-third-largest-ada-gpu-the-ad106-features-pcie-x8-interface
NVIDIA's Third Largest Ada GPU, the AD106, Features PCIe x8 Interface
It looks like NVIDIA is finally taking AMD's route in the mid-range by giving the third-largest silicon in its next-generation GeForce "Ada" RTX 40-series a narrower PCI-Express host interface. The AD106 silicon will be NVIDIA's third largest client GPU based on the "Ada" architecture, and succeeds the GA106 powering the likes of the GeForce RTX 3060. This chip reportedly features a narrower PCI-Express x8 host interface. At this point we don't know if the AD106 comes with PCI-Express Gen 5 or Gen 4. Regardless, having a PCIe lane count of 8 could possibly impact performance of the GPU on systems with PCI-Express Gen 3, such as 10th Gen Intel "Comet Lake," or even AMD's Ryzen 7 5700G APU.Interestingly, the same leak also claims that the AD107, the fourth largest silicon powering lower mid-range SKUs, and which succeeds the GA107, features the same PCIe lane-count of x8. This is unlike AMD, which gives the "Navi 24" silicon a PCI-Express 4.0 x4 interface. Lowering the PCIe lane count simplifies PCB design, since there are fewer PCIe lanes to be wired out in precise trace-lengths to avoid asynchrony. It also reduces the pin-count of the GPU package. NVIDIA's calculation here is that there are now at least two generations of Intel and AMD platforms with PCIe Gen 4 or later (Intel "Rocket Lake" and "Alder Lake," AMD "Zen 2," and "Zen 3,") and so it makes sense to lower the PCIe lane-count.
Original Link: https://www.techpowerup.com/298768/nvidias-third-largest-ada-gpu-the-ad106-features-pcie-x8-interface
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